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Ordering number:ENN4013A
CMOS IC
LC83015E
Digital Signal Processor for Audio Applications
Overview
The LC83015E is a digital signal processor IC designed for medium- and high-class home audio systems, such as AV amplifiers, mini, super-mini and car audio component systems. The LC83015E is a part of the LC83010N/NE family. It features an internal ROM, with a large standard program library, an internal RAM for user programs and a wide variety of interface capabilities. The standard program library includes sound-field simulation, theater surround and karaoke programs. The LC83015E operates from a 5V supply and is available in 80-pin QFPs. * Coefficient ROM. * Logarithmic conversion coefficients. * Audio interface. * 2 input channels compatible with a variety of formats. * 3 output channels compatible with a variety of 32/64fs formats. * External memory interface. * DRAM interface. 120 ns (maximum) RAS access time. 1Mbyte (256Kbyte x 4) or 256Kbyte (64Kbyte x 4). 1 or 2 units. * SRAM/ROM interface. 100 ns (maximum) address access time. 1Mbyte (128Kbyte x 8) or 256Kbyte (32Kbyte x 8). 1 unit. * Pseudo-SRAM interface. 70 ns (maximum) CE access time. 1Mbyte (128Kbyte x 8) or 256Kbyte (32Kbyte x 8). 1 unit.
Features
* 80 ns cycle time at fs = 48kHz (256 cycles/fs) * Dual-Harvard architecture allows single-cycle stereo signal integration and playback, with two of each of the following. * 24 x 16-bit fixed decimal point multiplier. * 32-bit arithmetic operation and 24-bit arithmetic logic operation ALU/shifter. * 32-bit accumulator. * 8 x 32-bit temporary storage registers. * 64 x 24-bit internal data RAM. * 128 x 16-bit internal coefficient RAM. * 304 x 16-bit internal coefficient ROM. * Large program memory. * 1024 x 32-bit standard program ROM. * 256 x 32-bit user program RAM. * Standard program ROM. * Sound-field simulation library. Auditorium simulation. Stereo, 3-band graphic equalizer. 12-band spectrum analyzer. * Karaoke function library. Pitch shift (realized in program RAM) Vocal mute. Microphone echo.
Package Dimensions
unit:mm 3174-QIP80E
[LC83015E]
23.2 20.0 0.8 64 65 1.6 0.8 0.35
1.0
41 40
0.15
17.2
14.0
0.8
1.6
80 1 24
25
3.0max 0.8
2.7
21.6
0.8
SANYO : QIP80E
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
80101TN (KT)/40893JN No.4013-1/13
15.6
LC83015E
* Maximum external memory access per sampling period. 42/32 access for 16- /24-bit, with 2 DRAMs. 51/36 access for 16- /24-bit, with 2 SRAM. 64/42 access for 16- /24-bit, with 1 pseudo- SRAM. * Serial microprocessor interface. * 8-bit. * Input and output synchronization control. * 8 x 16-bit LIFO register. * Other functions. * Interrupt input. * 4-level stack nesting. * 12-bit interval timer. * Compatible with LC83EV015 (PGA120) evaluation IC. * 5V supply voltage. * 80-pin QFP.
Pin Assignment
Top view
No.4013-2/13
LC83015E
Pin Description
Number 1 to 6 7 8 9 10 11 12 13, 51, 77 14 to 17 18, 33, 54, 74 19 20 21 22 23 24 25 to 32 34 to 50 52 53 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 75 76 78 79 80 Name P0 to P5 ASI1 BCK1 FS384I LRCKI ASI2 BCK2 VDD1 to VDD3 TEST1 to TEST4 VSS1 to VSS4 TEST5 RAS CAS DWRT DREAD CE/CS D7 to D0 A0 to A16 OSC1 OSC2 FS384O FS192O FS128O FS64O FS32O LRCKO AOWCK ASO AOTDF1 AOTDF2 SI SICK SIRQ SIAK SRDY SO SOCK SORQ SOAK RES INT SELC SACK1 SACK2 Audio data serial input 1 64fs or 32fs bit clock input for ASI1 384fs or 512fs input Left-/right-channel clock input Audio data serial input 2 64fs or 32fs bit clock input for ASI2 Supply voltage connections Test inputs. Connect to ground for normal operation. Ground connections Test output. Leave open for normal operation. DRAM interface RAS output DRAM interface CAS output Data write output Data read output External SRAM or pseudo-SRAM chip enable output External memory data bus External memory address bus Crystal oscillator input. Connect to VDD or VSS when not used. Crystal oscillator output. Leave open when not used. 384fs or 512fs output (Same as FS384I or OSC1/OSC2 clock) 192fs or 256fs output (1/2 of FS384O) 128fs output (1/3 or 1/4 of FS384O) 64fs or 32fs output (BCK1 of 1/2 of FS128O) 32fs or 16fs output (1/2 of FS64O) 1fs output (LRCKI or 1/64 of FS64O) 2fs or 1fs output (1/32 of FS64O) Audio data serial output 1 Audio data serial output 2 Audio data serial output 3 8-bit serial data input SI clock input Serial data input request input Serial data input acknowledge output Serial data input ready input 8-bit serial data output SO clock input Serial data output request input Serial data output acknowledge output Reset input. Internal pull-up resistor Interrupt request input. Internal pull-up resistor. Instrunction clock source selection input. Internal pull-down resistor. FS384O selection terminal. Internal pull-down resistor. Fs output clock source selection input. Internal pull-down resistor. Description General-purpose input/output port. Internal pull-up resistor
No.4013-3/13
LC83015E Specifications
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output voltage OSC2 output voltage Audio data and external memory interface output current SO, SOAK and SIAK output current P0 to P5 output current Allowable power dissipation Operating temperature Storage temperature Symbol
VDD1, VDD2, VDD3
Conditions
Ratings - 0.3 to +7.0 - 0.3 to VDD +0.3 - 0.3 to VDD +0.3 Up to approved oscillator voltage
Unit V V V V mA mA mA mW
C C
VI VO1 VO2 IO1 IO2 IO3 Pd max Topr Tstg See note 1.
- 2 to +4 - 2 to +10 - 1 to +10 700 - 30 to +70 - 40 to +125
Note 1. Pins ASO, AOTDF1, AOTDF2, FS384O, FS192O, FS128O, FS64O, FS32O, AOWCK, LRCKO, D0 to D7, A0 to A16, RAS, CAS, DREAD, DWRT and CE/CS Recommended Operating Conditions at Ta = -30 to +70C, VSS1 to VSS4 = 0V
Parameter Supply voltage range Symbol
VDD1, VDD2, VDD3
Conditions
Ratings 4.75 to 5.25
Unit V
Electrical Characteristics at Ta = -30 to +70C, VDD1 to VDD3 = 4.75 to 5.25 V, VSS1 to VSS4 = 0V
Parameter Current drain Audio data and external memory interface lowlevel input voltage Audio data and external memory interface highlevel input voltage Low-level input voltage High-level input voltage Serial interface low-level input voltage Serial interface high-level input voltage Low-level output voltage High-level output voltage RES and INT low-level input current P0 to P5 low-level input current Other low-level input current SELC, SACK1 and SACK2 high-level input current High-level input current RAS, CAS, DWRT, DREAD and CE/CS total output current D0 to D7 and A0 to A16 total output current Total output current Total output current Output leakage current Input capacitance Symbol IDD VIL1 VIH1 VIL2 VIH2 VIL3 VIH3 VOL VOH IIL1 IIL2 IIL3 IIH1 IIH2 IOA1 IOA2 IOA3 IOA4 IOFF CI Conditions 25MHz external clock. See note 8. See note 1. See note 1. See note 2. See note 2. See note 3. See note 3. IOL=2mA IOL=10mA IOH=- 0.4mA IOH=- 50A VI=VSS VI=VSS VI=VSS VI=VDD VI=VDD - 10 - 20 See note 6. See note 7. - 15 - 10 - 40 4.0
VDD- 1.2
0.75VDD
Ratings min typ 50 max 105 0.8 2.4 0.3VDD 0.7VDD
0.25VDD
Unit mA V V V V V V
0.4 1.5
V V A A A
- 250 - 1000 - 10 250 10 +10 +20 +15 +10 +40 10
A A mA mA mA mA A pF
Notes 1. Pins BCK1, BCK2, ASI1, ASI2, LRCKI and D0 to D7. Schmitt trigger inputs 2. Pins P0 to P5, TEST1 to TEST4, SELC, SACK1 and SACK2 3. Pins RES, INT, SI, SICK, SIRQ, SRDY, SOCK, SORQ, FS384I and OSC1. Schmitt trigger inputs 4. Pins ASO, AOTDF1, AOTDF2, FS384O, FS192O, FS128O, FS64O, FS32O, AOWCK, LRCKO, D0 to D7, A0 to A16, RAS, CAS, DREAD, DWRT and CE/CS. TTL-level outputs 5. Pins RAS, CAS, DWRT, DREAD and CE/CS 6. Pins FS384O, FS192O, FS128O, FS64O, FS32O, LRCKO, AOWCK, ASO and AOTDF1/2 7. Pins SIAK, SRDY, SO, SOAK and P0 to P5 8. See section DESIGN NOTES for measurement conditions.
No.4013-4/13
LC83015E
System Clock at Ta = -30 to +70C, VDD1 to VDD3 = 4.75 to 5.25 V, VSS1 to VSS4 = 0V
Parameter FS384I external clock frequency FS384I external clock low- and high-level pulsewidth FS384I external clock rise and fall time OSC1/OSC2 crystal oscillator frequency OSC1/OSC2 crystal oscillator stable delay Operating period Symbol fEXT fEXTL, fEXTH fEXTR, fEXTF fOSC fOSCS TCYC 79 Conditions Ratings min 12.16 16 9 24.83 100 169 typ max 24.83 Unit MHz ns ns MHz ms ns
External Clock Timing
Oscillator Stable Delay Time
Audio Data Interface at Ta = -30 to +70C, VDD1 to VDD3 = 4.75 to 5.25 V, VSS1 to VSS4 = 0V
Parameter Input bit clock period Input bit clock pulsewidth Data setup time Data hold time Output data propagation delay Output data hold time Symbol tBCYC tBCW tS tH tOD tOH 0 Conditions Ratings min 325 100 70 70 50 typ max Unit ns ns ns ns ns ns
Note Output timing values are measured with a load capacitance of 50 pF. Audio Data Input Timing
Audio Data Output Timing
No.4013-5/13
LC83015E
Serial Data Interface at Ta = -30 to +70C, VDD1 to VDD3 = 4.75 to 5.25 V, VSS1 to VSS4 = 0V
Parameter Serial clock period Serial clock pulsewidth Input data setup time Input data hold time Output data propagation delay Symbol tSCYC tSCW tSS tSH tSD Conditions Ratings min 480 200 70 70 100 typ max Unit ns ns ns ns ns
Note Output timing values are measured with a load capacitance of 50 pF. Serial Data Input Timing
Serial Data Output Timing
External DRAM Interface at Ta = -30 to +70C, VDD1 to VDD3 = 4.75 to 5.25 V, VSS1 to VSS4 = 0V
Parameter Input data setup time Input data hold time CAS low-level pulsewidth CAS high-level pulsewidth RAS low-level pulsewidth RAS high-level pulsewidth CAS period RAS to CAS propagation delay CAS hold time RAS hold time RAS address setup time RAS address hold time CAS address setup time CAS address hold time DWRT pulsewidth Write command setup time Write command hold time Output data setup time Output data hold time Symbol tDSI1 tDHI1 tCAS tCP tRAS tRP tPC tRCD tCSH tRSH tASR tRAH tASC tCAH tWP tWCS tWCH tDSO1 tDHO1 Conditions Ratings min 15 0 75 75 350 110 160 110 190 70 140 30 70 70 75 30 30 50 50 typ max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note Output timing values are measured with a load capacitance of 50 pF.
No.4013-6/13
LC83015E
External DRAM Input Timing
External DRAM Output Timing
External SRAM Interface at Ta = -30 to +70C, VDD1 to VDD3 = 4.75 to 5.25 V, VSS1 to VSS4 = 0V
Parameter Input data setup time Input data hold time Read/write cycle time Address setup time Write recovery time DWRT pulsewidth Output data setup time Output data hold time Symbol tDSI2 tDHI2 tRWC tAS tWR tWP tDSO2 tDHO2 Conditions Ratings min 60 0 160 10 30 75 50 30 typ max Unit ns ns ns ns ns ns ns ns
Note Output timing values are measured with a load capacitance of 50 pF.
No.4013-7/13
LC83015E
External SRAM Input Timing
External SRAM Output Timing
External Pseudo-SRAM Interface at Ta = -30 to +70C, VDD1 to VDD3 = 4.75 to 5.25 V, VSS1 to VSS4 = 0V
Parameter Input data setup time Input data hold time CE/CS period CE/CS pulsewidth CE/CS pre-charge time CE/CS address setup time CE/CS address hold time Write command hold time Write command read time DWRT pulsewidth DWRT output data setup time DWRT output data hold time CE/CS output data setup time CE/CS output data hold time CE/CS to DREAD propagation delay Symbol tDSI3 tDHI3 tC tCES tP tASC tAHC tWCH tCWL tWP tDSW tDHW tDSC tDHC tDER Conditions Ratings min 10 0 160 75 75 15 100 70 70 75 50 30 50 30 0 30 typ max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note Output timing values are measured with a load capacitance of 50 pF.
No.4013-8/13
LC83015E
External Pseudo-SRAM Input Timing
External Pseudo-SRAM Output Timing
Design Notes When SELC is LOW, the LC83015E system clock is generated from FS384I. When SELC is HIGH, it is generated from the free-running oscillator, OSC1. When SACK1 is LOW, FS384O output is 1/3 of FS128O output. When SACK1 is HIGH, it is 1/4 of FS128O output. When SACK2 is LOW, the output clock is generated from FS384I, LRCKI and BCK1. When SACK2 is HIGH, it is generated from the free-running oscillator, OSC1.
When the LC83015E is used with one DRAM unit, only D0 to D3 of the data bus are used. When the LC83015E is used with two DRAM units, SRAM or pseudo-SRAM, D0 to D7 are used. The typical supply current, IDD, is measured with SANYO Standard Theatre Mode in operation under the input/output conditions shown in figure 1.
No.4013-9/13
LC83015E
Figure 1. Measurment conditions for IDD
No.4013-10/13
LC83015E
The LC83015E has three voltage supply pins (VDD1 to VDD3) and four ground pins (VSS1 to VSS4). The connections between these pins must conduct sufficiently to ensure that there are no voltage differences between each of the voltage supply pins and each of the ground pins when the device is powered-up. Connections similar to those shown in figure 2 should be used. Figure 3 shows the connection of a crystal oscilator to the LC83015E Table 1 shows oscillator frequencies and capacitances for a Nippon Denpa Kogyo NR-18 crystal oscillator.
Figure 3. Crystal oscillator connection Table 1. Oscillator frequency selection
C1, C2 (pF) 18 12 10 12 8 6 Oscillator frequency (MHz) 12.288 16.9344 18.432 16.834 22.5792 24.576
Figure 2. Voltage supply and ground connection template
No.4013-11/13
LC83015E
LC83015E Development Environment The following software tools are available. * LC83015.EXE assembler * S83015.EXE debugger and simulator * STI.EXE ROM sorting software for microprocessor * STO.EXE ROM sorting software for external ROM The following hardware tools are intended for use with the LC83015E. * IBM PC/AT or AX personal computer * In-Circuit Emulator (ICE) comprising ICE83015 POD83 IC149-080-021-S5 E83015.EXE software * Simple model evaluation board comprising PRBD15 D2SP.EXE software
Figure 4. ICE configuration
Figure 5. Model board configuration
No.4013-12/13
LC83015E
Application Example
Note The LC83015E is in external synchronization mode in this application.
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of August, 2001. Specifications and information herein are subject to change without notice.
PS No.4013-13/13

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